
BIT1612 10-Bit Digital Video Decoder with OSD and T-CON
74
自動辦別 NTSC/PAL Mode 並可由 Register (0x16A[1]) 直接讀出其狀態。
5. EVEN/ODD Type Detection:
自動判別 VSYNC 是否有 EVEN/ODD 相關變化,並可由 Register (0x16A[2]) 直接讀出其狀態。
6. Data Enable Signal Detection:
自動偵測 Data Enable Signal Information 以供系統作為設定 Input Windows 的參考。
7. No Signal Detection:
自動判別 HSYNC 是否有 Toggle,如果在 2047 XCLKs 內沒有變化將由 Interrupt (0x002[1:0]) 回應或
可由 Register (0x16A[3]) 直接讀出其狀態。
Table 6-69 Auto Detection Register
Mnemonic Address R/W Bits Description Default
R_IS_XP 0x160[7:0] R 8
HSYNC Low Pulse
(Base on PCLK)
-
R_IS_XT 0x164[7:4], 0x161[7:0] R 12
HSYNC Total Width
(Base on PCLK)
-
R_IS_YP 0x162[7:0] R 8
VSYNC Low Pulse
(Base on HSYNC)
-
R_IS_YT 0x164[2:0], 0x163[7:0] R 11
VSYNC Total width
(Base on HSYNC)
-
R_DET_XP 0x167[7:4],0x165[7:0] R 12
HSYNC High Level Width
(Base on XCLK)
-
R_DET_XN 0x167[3:0],0x166[7:0] R 12
HSYNC Low Level Width
(Base on XCLK)
-
R_HOUNT 0x169[6:0],0x168[7:0] R 15
Line Buffer Overflow/Underflow
Count
-
R_MODECHG 0x16A[0] R 1
Mode Change Status
Î0: No Mode Change
Î1: VSYNC Variation Larger than 8
HSYNCs
-
R_MODE_TYPE 0x16A[1] R 1
Mode Status
Î0: 50Hz
Î1: 60Hz
-
R_EVENSAME 0x16A[2] R 1
EVEN Type Status
Î0: Had EVEN/ODD Information
Î1: No EVEN/ODD Information
-
R_SIGIN 0x16A[3] R 1
Sync Status
Î0: Signal Ready
Î1: No Signal
-
R_AUTOON 0x16A[4] R 1
Auto Blank Status
Î0: Normal Mode
Î1: Free-Run Mode
-
R_SWITCH 0x16A[5] R 1
Auto Switch Status
Î0: Mode 0
Î1: Mode 1
-
R_EVEN 0x16A[6] R 1
EVEN/ODD Information
Î0: EVEN Field
Î1: ODD Field
-
R_IDE_INFO 0x16C[3:0],0x16B[7:0] R 12 Input Data Enable Information -
Input Data Enable Mode Selection
00: HSYNC Low Pulse Information
01: HSYNC High Pulse Information
10: VSYNC Low Pulse Information
R_IDE_DET 0x4E[1:0] RW 2
11: VSYNC High Pulse Information
00
Input Data Enable Source Selection R_IDE_SEL 0x4E[3:2] RW 2
00: From HSYNC1 Pin
00
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