
BIT1612 10-Bit Digital Video Decoder with OSD and T-CON
41
10: Synchronized with
Output VSYNC
0x: Not Synchronized with VSYNC
Panel clock
R_PWM_REF
Reference clock
Base on panel clock
R_PWM_FREQ
R_PWM_DUTY
PWM Output
Base on reference clock
Figure 6-26 PWM Function
6.28 Video Decoder
6.28.1 Video Decoder Feature
y Three analog inputs, internal analog source selectors, e.g. CVBS x3 or Y/C x1 or ( Y/C x1 and CVBS x1)
or YPbPr (480i or 576i)
y Two 10-bit video CMOS Analog-to-Digital Converters (ADCs) in differential CMOS style for best
S/N-performance
y Fully programmable static gain or automatic gain control (AGC) for the selected CVBS or Y/C channel :
0~12db (Analog) and 0~18db (Digital)
y Automatic Clamp Control (ACC) for CVBS, Y and C
y On-chip clock generator
y Digital PLL for synchronization and clock generation from all standards and non-standard video sources
e.g. consumer grade VTR
y Requires only one crystal (24.576 MHz) for all standards
y Automatic detection of 50 and 60 Hz field frequency, and automatic switching between PAL and NTSC
standards
y Accepts NTSC (J, M, 4.43), PAL (60, B, D, G, H, I, M, N), and SECAM (B, D, G, K, K1, L) video signal
y User programmable luminance peaking or aperture correction
y Adaptive 3/5-line comb filter for two dimensional chrominance/luminance separation
y PAL delay line for correcting PAL phase errors
y Brightness Contrast Saturation (BCS) and Hue control on-chip
y Multi-standard VBI-data slicer decoding closed caption
y MV copy protection detection
y User programmable sharpness filter
y User programmable U/V Gain and CTI function
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